STM32F401 Black Pill...
The STM32F401 'Black pill' development board is an updated version of the original F103 based...
- Currently Out of Stock
16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline
Extended instruction set
Medium-density Flash/EEPROM: Program memory up to 32 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles Data memory up to 1Kbytes true data EEPROM; endurance 300 kcycles
RAM: Up to 2 Kbytes...
Further information including example sketch, schematic etc is available on our support forum.
16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline
Extended instruction set
Medium-density Flash/EEPROM: Program memory up to 32 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles Data memory up to 1Kbytes true data EEPROM; endurance 300 kcycles
RAM: Up to 2 Kbytes
2.95 to 5.5 V operating voltage
Flexible clock control, 4 master clock sources: Low power crystal resonator oscillator External clock input Internal,user-trimmable 16 MHz RC Internal low power 128 kHz RC
Clock security system with clock monitor
Power management: Low power modes (wait, active-halt, halt) Switch-off peripheral clocks individually
Permanently active,low consumption power-on and power-down reset
Nested interrupt controller with 32 interrupts
Up to 37 external interrupts on 6 vectors
2x16-bit general purpose timer, with 2+3 CAPCOM channels (IC, OC or PWM)
Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
8-bit basic timer with 8-bit prescaler
Window watchdog, independent watchdog timers
UART with clock output for synchronous operation, Smartcard, IrDA, LIN master mode
SPI interface up to 8 Mbit/s
I2C interface up to 400 Kbit/s
10-bit, ±1 LSB ADC with up to 10 multiplexed channels, scan mode and analog watchdog
Up to 38 I/Os on a 48-pin package including 16 high sink outputs
Highly robust I/O design, immune against current injection
Embedded single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging
96-bit unique ID key for each device
Further information including example sketch, schematic etc is available on our support forum.
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